Methods of packaging semiconductor devices and packaged semiconductor devices

ABSTRACT

Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes coupling through-vias to an insulating material, each of the through-vias having a first width. Dies are also coupled to the insulating material. A portion of the insulating material is removed proximate each of the through-vias. The portion of the insulating material proximate each of the through-vias removed has a second width, the second width being less than the first width.

BACKGROUND

Semiconductor devices are used in a variety of electronic applications,such as personal computers, cell phones, digital cameras, and otherelectronic equipment, as examples. Semiconductor devices are typicallyfabricated by sequentially depositing insulating or dielectric layers,conductive layers, and semiconductive layers of material over asemiconductor substrate, and patterning the various material layersusing lithography to form circuit components and elements thereon.

Dozens or hundreds of integrated circuits are typically manufactured ona single semiconductor wafer. The individual dies are singulated bysawing the integrated circuits along a scribe line. The individual diesare then packaged separately, in multi-chip modules, or in other typesof packaging, for example.

The semiconductor industry continues to improve the integration densityof various electronic components (e.g., transistors, diodes, resistors,capacitors, etc.) by continual reductions in minimum feature size, whichallow more components to be integrated into a given area. These smallerelectronic components such as integrated circuit dies also requiresmaller packages that utilize less area than packages of the past, insome applications.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIGS. 1 through 16 are cross-sectional views illustrating a method ofpackaging a semiconductor device at various stages in accordance withsome embodiments of the present disclosure.

FIGS. 17 and 18 are cross-sectional views of a packaged semiconductordevice coupled to another packaged semiconductor device in accordancewith some embodiments.

FIG. 19 is a cross-sectional view of a more detailed portion of thepackaged semiconductor device shown in FIG. 15 in accordance with someembodiments.

FIG. 20 is a cross-sectional view illustrating a shear force test of asolder ball in accordance with some embodiments.

FIGS. 21 and 22 are top views and cross-sectional views, respectively,of portions of a packaged semiconductor device in accordance with someembodiments.

FIG. 23 is a cross-sectional view illustrating a packaged semiconductordevice in accordance with some embodiments.

FIG. 24 is a flow chart illustrating a method of packaging asemiconductor device in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

Embodiments of the present disclosure provide novel methods of packagingsemiconductor devices and structures thereof, wherein openings in aninsulating material layer have a smaller width than a width ofthrough-vias of the package. The openings with reduced width improvereliability of the package, eliminate recesses and drilling gaps inadjacent molding material layers, and prevent water vapor penetration,to be described further herein.

FIGS. 1 through 16 are cross-sectional views illustrating a method ofpackaging a semiconductor device at various stages in accordance withsome embodiments of the present disclosure. Referring first to FIG. 1,to package the semiconductor device, a carrier 100 is provided. Thecarrier 100 may comprise glass, silicon oxide, aluminum oxide, or asemiconductor wafer, as examples. The carrier 100 may also compriseother materials. The carrier may be circular, square, or rectangular ina top view, as examples. Alternatively, the carrier 100 may compriseother shapes.

The carrier 100 has a film 102 formed thereon in some embodiments. Thefilm 102 comprises a light to heat conversion (LTHC) material or othermaterials, for example. The LTHC film 102 comprises a thickness of about0.5 μm to about 3 μm, for example. Alternatively, the film 102 maycomprise other dimensions. In some embodiments, the film 102 is notincluded.

To package a semiconductor device, an insulating material 104 isdisposed over the film 102, as shown in FIG. 1. The insulating material104 is formed over the carrier 100 in embodiments wherein the film 102is not included. The insulating material 104 comprises a passivationlayer for the package. The insulating material 104 comprises aglue/polymer base buffer layer in some embodiments, for example. Theinsulating material 104 comprises a solder resist (SR), polyimide (PI),polybenzoxazole (PBO), or multiple layers or combinations thereof insome embodiments, as examples. The insulating material 104 comprises athickness of about 1 μm to about 20 μm, for example. Alternatively, theinsulating material 104 may comprise other materials and dimensions. Theinsulating material 104 is formed using spin coating, lamination, orother methods, for example.

Next, a seed layer 106 is formed over the insulating material 104, asshown in FIG. 2. The seed layer 106 comprises a seed material for asubsequent plating process for through-vias, to be described furtherherein. The seed layer 106 comprises a metal, such as copper, a titaniumand copper alloy, other metals, alloys, combinations or multiple layersthereof, as examples. The seed layer 106 comprises a thickness of about500 Angstroms to about 5,000 Angstroms, for example. Alternatively, theseed layer 106 may comprise other materials and dimensions. The seedlayer 106 is formed by physical vapor deposition (PVD) or other methods.

A sacrificial material 108 is then formed over the seed layer 106, asshown in FIG. 3. The sacrificial material 108 comprises a photoresist,an organic material, an insulating material, or other materials, in someembodiments, as examples. The sacrificial material 108 is patterned witha desired pattern for a plurality of through-vias using a lithographyprocess or a direct patterning process, as shown in FIG. 4. In alithography process, the sacrificial material 108 comprising aphotoresist or other material is exposed to light or energy reflectedfrom or transmitted through a lithography mask (not shown) that has thedesired pattern thereon. The sacrificial material 108 is then developed,and portions of the sacrificial material 108 are then ashed or etchedaway. A direct patterning process may comprise forming the pattern inthe sacrificial material 108 using a laser, for example. Alternatively,the sacrificial material 108 may be patterned using other methods.

A plating process is used to form a conductive material 112 in thepatterns of the sacrificial material 108 over the seed layer 106, asshown in FIG. 5. The plating process may comprise an electro-chemicalplating (ECP) or other types of plating processes, for example. The seedlayer 106 functions as a seed for the plating process for the conductivematerial 112. The conductive material 112 is plated over the seed layer106 through the patterned sacrificial material 108.

The sacrificial material 108 is then stripped or removed, as shown inFIG. 6. After the sacrificial material 108 is removed, portions of theseed layer 106 are left remaining over the insulating material 104between the conductive material 112 that has been plated onto the seedlayer 106.

The exposed portions of the seed layer 106 are then removed, as shown inFIG. 7. An etch process or other process is used to remove the exposedportions of the seed layer 106 between the regions of conductivematerial 112, for example. The seed layer 106 and the conductivematerial 112 comprise through-vias 106/112 of a package for asemiconductor device. The through-vias 106/112 each comprise a lowerportion comprising the material of the seed layer 106 and an upperportion comprising the plated-on conductive material 112.

In other embodiments, the through-vias 106/112 may be formed usingsubtractive techniques, damascene techniques, or other methods. Forexample, in a subtractive technique, a conductive material such as Cu, aCu alloy, other metals, or combinations or multiple layers thereof maybe formed over the entire surface of the insulating material 104, andthe conductive material is patterned to form the through-vias 106/112.The through-vias 106/112 may comprise a single material layer in theseembodiments, for example, not shown. The conductive material may bepatterned using photolithography, by forming a layer of photoresist overthe conductive material, exposing the layer of photoresist to light orenergy reflected from or transmitted through a lithography mask having adesired pattern thereon, and developing the layer of photoresist.Exposed (or unexposed, depending on whether the layer of photoresist ispositive or negative) portions of the layer of photoresist are thenashed and removed. The patterned layer of photoresist is then used as anetch mask during an etch process for the conductive material. The layerof photoresist is removed, leaving the conductive material patternedwith the desired pattern of the through-vias 106/112.

A first side of the through-vias 106/112 is coupled to the insulatingmaterial 104 in some embodiments, for example.

Referring next to FIG. 8, after the formation of the through-vias106/112, a plurality of integrated circuit dies 120 are provided and arebonded to the insulating material 104. The integrated circuit dies 120are also referred to herein, e.g., in some of the claims, as dies 120.The integrated circuit dies 120 comprise semiconductor devices that willbe packaged in accordance with some embodiments of the presentdisclosure. The integrated circuit dies 120 may be previously fabricatedon one or more semiconductor wafers, and the wafer or wafers aresingulated or diced to form a plurality of the integrated circuit dies120, for example.

The integrated circuit dies 120 include a substrate 122 comprising asemiconductive material and that includes circuitry, components, wiring,and other elements (not shown) fabricated within and/or thereon. Theintegrated circuit dies 120 are adapted to perform a predeterminedfunction or functions, such as logic, memory, processing, otherfunctions, or combinations thereof, as example. The integrated circuitdies 120 are typically square or rectangular in shape in a top view, notshown. The integrated circuit dies 120 each include a first side 128 aand a second side 128 b, the second side 128 b being opposite the firstside 128 a. The first sides 128 a of the integrated circuit dies 120 arecoupled to the insulating material 104.

The integrated circuit dies 120 each include a plurality of contact pads124 formed across the second side 128 b thereof. The contact pads 124are electrically coupled to portions of the substrate 122. The contactpads 124 comprise a conductive material such as copper, aluminum, othermetals, or alloys or multiple layers thereof, as examples.Alternatively, the contact pads 124 may comprise other materials.

The contact pads 124 are disposed within an insulating material 126formed over the substrate 122. Portions of the top surfaces of thecontact pads 124 are exposed within the insulating material 126 so thatelectrical connections can be made to the contact pads 124. Theinsulating material 126 may comprise one or more insulating materiallayers, such as silicon dioxide, silicon nitride, a polymer material, orother materials. The insulating material 126 comprises a passivationlayer in some embodiments, for example.

A plurality of the integrated circuit dies 120 are coupled to thecarrier 100 over the insulating material 104. Only two integratedcircuit dies 120 are shown in FIGS. 8 through 16; however, dozens,hundreds, or more integrated circuit dies 120 may be coupled to thecarrier 100 and packaged simultaneously. The first sides 128 a of theintegrated circuit dies 120 are coupled to the carrier 100, over theinsulating material 104. The integrated circuit dies 120 may be coupledto the insulating material 104 using an adhesive such as a die attachfilm (DAF), for example. The integrated circuit dies 120 may be coupledto the insulating material 104 manually or using an automated machinesuch as a pick-and-place machine.

In some embodiments, the integrated circuit dies 120 are coupled to theinsulating material 104 disposed on the carrier 100, and the integratedcircuit dies 120 are packaged in individual packages. In otherembodiments, two or more integrated circuit dies 120 can be packagedtogether. A plurality of integrated circuit dies 120 comprising the sameor different functions may be packaged together in accordance with someembodiments, for example.

A molding material 130 is then disposed over and around the integratedcircuit dies 120 and the through-vias 106/112, as shown in FIG. 9. Themolding material 130 is applied using a wafer level molding process insome embodiments, for example. The molding material 130 is formed overexposed portions of the insulating material 104, over the sidewalls ofthe integrated circuit dies 120, over exposed portions of the secondsides 128 b of the integrated circuit dies 120, and over the sidewallsand top surfaces of the through-vias 106/112. The molding material 130is formed around the plurality of through-vias 106/112, around theplurality of dies 120, and between the plurality of through-vias 106/112and the plurality of dies 120, for example. A first side of the moldingmaterial 130 is coupled to the insulating material 104 in someembodiments.

The molding material 130 may be molded using, for example, compressivemolding, transfer molding, or other methods. The molding material 130encapsulates the integrated circuit dies 120 and the through-vias106/112, for example. The molding material 130 may comprise an epoxy, anorganic polymer, a polymer with or without a silica-based or glassfiller added, or other materials, as examples. In some embodiments, themolding material 130 comprises a liquid molding compound (LMC) that is agel type liquid when applied. The molding material 130 may also comprisea liquid or solid when applied. Alternatively, the molding material 130may comprise other insulating and/or encapsulating materials.

Next, the molding material 130 is cured using a curing process in someembodiments. The curing process may comprise heating the moldingmaterial 130 to a predetermined temperature for a predetermined periodof time, using an anneal process or other heating process. The curingprocess may also comprise an ultra-violet (UV) light exposure process,an infrared (IR) energy exposure process, combinations thereof, or acombination thereof with a heating process. Alternatively, the moldingmaterial 130 may be cured using other methods. In some embodiments, acuring process is not included.

A top portion of the molding material 130 is then removed, as shown inFIG. 10. The top portion of the molding material 130 is removed using agrinding process in some embodiments, for example. The grinding processmay comprise a process similar to a sanding process that is used forwood, using a rotating sander, for example. The grinding process maycomprise rotating a disk lined with an appropriate material or materialsfor grinding the materials of the molding material 130 to apredetermined height, for example. The disk may be lined with diamond,for example. In some embodiments, a chemical-mechanical polishing (CMP)process is used to remove the top portion of the molding material 130,for example. A combination of a grinding process and a CMP process mayalso be used. The CMP process or grinding process may be adapted to stopwhen the second sides 128 b of the integrated circuit dies 120 and/orthe top surfaces of the through-vias 106/112 are reached in someembodiments, for example. The CMP process and/or grinding processcomprises a front-side grinding process in some embodiments.

In some embodiments, a grinding or CMP process is not required. Themolding material 130 may be applied so that the molding material 130reaches a level that is substantially the same as the level of thesecond sides 128 b of the integrated circuit dies 120 and top surfacesof the through-vias 106/112 in some embodiments, for example. In someembodiments, the molding material 130 top surface may reside below thesecond sides 128 b of the integrated circuit dies 120 and the topsurfaces of the through-vias 106/112 after the application of themolding material 130, as another example, not shown.

In some embodiments, the top surface of the molding material 130 afterthe grinding and/or CMP process, or after the molding material 130deposition process, is substantially coplanar with the second sides 128b of the integrated circuit dies 120 and the top surfaces of thethrough-vias 106/112. The molding material 130 being substantiallycoplanar with the second sides 128 b and the top surfaces of thethrough-vias 106/112 advantageously facilitates in the formation of asubsequently formed interconnect structure 132, which is illustrated inFIG. 11. The top surfaces of the molding material 130, integratedcircuit dies 120, and the through-vias 106/112 comprise a substantiallyplanar surface for the formation of the interconnect structure 132 insome embodiments, for example.

The interconnect structure 132 is formed over a second side of theplurality of through-vias 106/112, the second side being opposite thefirst side of the plurality of through-vias 106/112 that is coupled tothe insulating material 104. Likewise, the interconnect structure 132 isformed over a second side of the molding material 130, the second sidebeing opposite the first side of the molding material 130 that iscoupled to the insulating material 104. Similarly, the interconnectstructure 132 is formed over a second side 128 b of the integratedcircuit dies 120, the second side 128 b being opposite the first side128 a of the integrated circuit dies 120.

The interconnect structure 132 comprises a post-passivation interconnect(PPI) structure or a redistribution layer (RDL) in some embodiments thatis formed over the plurality of integrated circuit dies 120, the moldingmaterial 130, and the top surfaces of the through-vias 106/112, forexample. The interconnect structure 132 includes fan-out regions thatexpand a footprint of contact pads 124 on the integrated circuit dies120 to a larger footprint for the package in some embodiments, forexample. The interconnect structure 132 includes a plurality ofdielectric layers 132D, and a plurality of conductive metal lines 132Mand/or a plurality of conductive metal vias (not shown) formed insidethe plurality of dielectric layers 132D. The plurality of conductivelines 132M and the plurality of conductive vias provide electricalconnections to contact pads 124 on the substrate 122 of the integratedcircuit dies 120. Two wiring levels are shown in FIGS. 11 through 16;alternatively, one wiring level or three or more wiring levels may beincluded in the interconnect structure 132.

The dielectric layers 132D may be formed, for example, of a lowdielectric constant (low-K) dielectric material, such as phosphosilicateglass (PSG), borophosphosilicate glass (BPSG), fluorinated silicateglass (FSG), SiOxCy, spin-on-glass, spin-on-polymers, silicon carbonmaterial, compounds thereof, composites thereof, combinations thereof,or the like, by any suitable method, such as spinning, CVD, and/orplasma-enhanced CVD (PECVD). The conductive lines 132M and conductivevias may comprise copper, copper alloys, other metals or alloys, orcombinations or multiple layers thereof, as examples. The conductivelines 132M and conductive vias may be formed using subtractive and/ordamascene techniques, as examples. The conductive lines 132M andconductive vias may be formed using one or more sputtering processes,photolithography processes, plating processes, and photoresist stripprocesses, as examples. Other methods can also be used to form theinterconnect structure 132. The interconnect structure 132 includescontact pads 132C formed proximate a top surface. The contact pads 132Cmay comprise under-ball metallization (UBM) structures in someembodiments that are arranged in a ball grid array (BGA) or otherpatterns or arrangements.

In some embodiments, a plurality of connectors 134 are then coupled tothe contact pads 132C of the interconnect structure 132, as shown inFIG. 12. The connectors 134 may comprise a eutectic material such assolder, for example. The eutectic material may comprise solder balls orsolder paste in some embodiments that is reflowed by heating theeutectic material to a melting temperature of the eutectic material. Theconnectors 134 are attached using a ball mount process or other process.The eutectic material is then allowed to cool and re-solidify, formingthe connectors 134. The connectors 134 may include other types ofelectrical connectors, such as microbumps, controlled collapse chipconnection (C4) bumps, or pillars, and may include conductive materialssuch as Cu, Sn, Ag, Pb, or the like. In some embodiments, the connectors134 are not included on the package. A test of the connectors 134 isthen conducted in some embodiments, to ensure electrical and structuralintegrity of the connections made.

In some embodiments, an insulating material is formed between theconnectors 134 over the interconnect structure 132, not shown. Theinsulating material comprises a LMC in some embodiments. The insulatingmaterial may alternatively comprise other materials. In otherembodiments, the insulating material is not included.

The carrier 100 and structures formed thereon described herein are theninverted, and the connectors 134 are coupled to a dicing tape 136, asshown in FIG. 13. The dicing tape 136 is coupled to a support 138. Thecarrier 100 and film 102 are then removed, also shown in FIG. 13, usinga de-bonding process.

In some embodiments, a protective film 140 is formed over the insulatingmaterial 104, as shown in FIG. 14. The protective film 140 is formedafter the carrier 100 is removed in some embodiments, for example. Theprotective film 140 comprises a back side lamination film in someembodiments, for example. The protective film 140 comprises about 1 μmto about 100 μm of a lamination coating (LC) tape or DAF, as examples.The protective film 140 is formed using a laminating process in someembodiments. The protective film 140 may also comprise other materials,dimensions, and formation methods. In some embodiments, the laminationfilm 140 is not included.

The insulating material 104 is then patterned, as shown in FIG. 15. Inembodiments wherein the lamination film 140 is included, the laminationfilm 140 is also patterned, as shown in FIG. 23, to be described furtherherein.

Referring next to FIG. 15, in accordance with some embodiments of thepresent disclosure, a portion of the insulating material 104 proximateeach of the plurality of through-vias 106/112 is then removed. Theportion of the insulating material 104 that is removed comprisesopenings 142, wherein an opening 142 is formed over each of thethrough-vias 106/112. The portions of the insulating material 104comprise a width that is less than a width of the through-vias 106/112in some embodiments. For example, the openings 142 in the insulatingmaterial 104 comprise a width that is less than a width of thethrough-vias 106/112 in some embodiments.

The portions of the insulating material 104 are removed using a laser insome embodiments. Alternatively, the portions of the insulating material104 may be removed using other methods, such as photolithography. Theopenings 142 in the insulating material 104 may be formed using alithography process or a direct patterning method, as examples.Alternatively, other methods may be used to remove the portions of theinsulating material 104 proximate the plurality of through-vias 106/112.A portion of each of the through-vias 106/112 is left exposed throughthe openings 142 in the insulating material 104. Other portions of eachof the through-vias 106/112 (e.g., edge portions) remain covered by theinsulating material 104. The portions of the through-vias 106/112 thatremain covered by the insulating material 104 are also referred toherein as first portions, and the portions of the through-vias 106/112that are exposed through the openings 142 in the insulating material 104are also referred to herein as second portions, e.g., in the some of theclaims. A more detailed view of two through-vias 106/112 is shown inFIG. 19, which will be described further herein.

In some embodiments, a solder paste 144 is then formed on the exposedportions of the through-vias 106/112, as shown in FIG. 16. The solderpaste 144 facilitates in coupling the packaged semiconductor device 150to another device, such as another packaged semiconductor device, usingconnectors (see connectors 158 in FIG. 17). The packaged semiconductordevices 150 are singulated or diced on scribe line regions to form aplurality of packaged semiconductor devices 150 in some embodiments. Forexample, the molding material 130, the interconnect structure 132, andthe insulating material 104 are diced along the scribe lines to form aplurality of the packaged semiconductor devices 150 in some embodiments,for example. In other embodiments, the packaged semiconductor devices150 are singulated later, after attaching them to other packagedsemiconductor devices 160, as shown in FIG. 17.

Two integrated circuit dies 120 are shown being packaged together in theembodiments shown in FIGS. 1 through 16, for example. Alternatively,three or more integrated circuit dies 120 can be packaged in a packagedsemiconductor device 150. Portions of the interconnect structure 132 mayprovide horizontal electrical connections for a plurality of theintegrated circuit dies 120 that are packaged together. For example,some of the conductive lines 132M and vias may comprise wiring betweenthe two or more of the integrated circuit dies 120. The molding material130 is disposed around and between the plurality of integrated circuitdies 120. The interconnect structure 132 is disposed over the pluralityof integrated circuit dies 120 and the molding material 130. Integratedcircuit dies 120 can also be packaged singly within a packagedsemiconductor device 150, as shown in FIGS. 17 and 18 in cross-sectionalviews.

FIGS. 17 and 18 also illustrate a packaged semiconductor device 150described herein coupled to another packaged semiconductor device 160 inaccordance with some embodiments. The packaged semiconductor device 150comprises a first packaged semiconductor device 150 in some embodiments,and the first packaged semiconductor device 150 is coupled to a secondpackaged semiconductor device 160 by a plurality of connectors 158. Theconnectors 158, which may comprise solder balls or other materials, arecoupled between through-vias 106/112 of the first packaged semiconductordevice 150 and contact pads of the second packaged semiconductor device160, for example. Each of a plurality of the connectors 158 is coupledto one of the plurality of through-vias 106/112 of the first packagedsemiconductor device 150 through the insulating material 104.

An intermetallic compound (IMC) 159 is formed between the connectors 158and a material of the through-vias 106/112 such as copper and/or thesolder paste 144 formed on the through-vias 106/112 (see FIG. 16) insome embodiments, when the connectors 158 are coupled to thethrough-vias 106/112. In some embodiments, the packaged semiconductordevice 170 that includes the first packaged semiconductor device 150 andthe second packaged semiconductor device 160 comprises apackage-on-package (PoP) device, for example.

The packaged semiconductor device 150 includes a plurality of thethrough-vias 106/112 formed within the molding material 130. Thethrough-vias 106/112 provide vertical connections for the packagedsemiconductor device 150. The interconnect structure 132 provideshorizontal electrical connections for the packaged semiconductor device150. The second packaged semiconductor device 160 also includes aninterconnect structure 132′ that provides horizontal electricalconnections for the packaged semiconductor device 160. Interconnectstructure 132′ of the second packaged semiconductor device 160 iscoupled to the through-vias 106/112 of the first packaged semiconductordevice 150 by a plurality of the connectors 158.

The second packaged semiconductor device 160 includes one or moreintegrated circuit dies 156 coupled to a substrate. In some embodiments,the dies 156 comprise memory chips. For example, the dies 156 maycomprise dynamic random access memory (DRAM) devices in someembodiments. Alternatively, the dies 156 may comprise other types ofchips. Wire bonds 152 may be coupled to contact pads on a top surface ofthe integrated circuit die or dies 156, which are coupled to bond padson the substrate. The wire bonds 152 provide vertical electricalconnections for the packaged semiconductor device 160 in someembodiments, for example. A molding material 162 may be disposed overthe wire bonds 152, the integrated circuit die or dies 156, and thesubstrate.

Alternatively, a PoP device 170 may include two packaged semiconductordevices 150 described herein that are coupled together in someembodiments, not shown in the drawings. In some embodiments, the PoPdevice 170 may comprise a system-on-a-chip (SOC) device, as anotherexample.

In some embodiments, an insulating material 164 is disposed between thepackaged semiconductor devices 150 and 160 between the connectors 158,as shown in FIG. 18 in a cross-sectional view. The insulating material164 may comprise an underfill material or a molding material, asexamples. Alternatively, the insulating material 164 may comprise othermaterials, or the insulating material 164 may not be included.

FIG. 19 is a cross-sectional view of a more detailed portion of FIG. 15in accordance with some embodiments. Some dimensions and shapes of theopenings 142 and 142′ in the insulating material 104 in accordance withsome embodiments are illustrated. The sidewalls of the openings 142 inthe insulating material 104 may comprise a tapered shape 146 in someembodiments. In other embodiments, the sidewalls of the openings 142′ inthe insulating material 104 may comprise a stair-stepped shape 146′.

The through-vias 106/112 comprise a width comprising dimension d₁,wherein dimension d₁ comprises about 190 μm to about 210 μm, in someembodiments. Dimension d₁ comprises about 300 μm or less in someembodiments, for example. Alternatively, dimension d₁ may comprise othervalues, such as greater than about 300 μm. The openings 142 and 142′comprise a width comprising dimension d₂, wherein dimension d₂ is lessthan dimension d₁, in some embodiments. Dimension d₂ comprises about 10%less or greater than dimension d₁ in some embodiments, for example. Inother embodiments, dimension d₂ comprises about 10% to 30% less thandimension d₁, as another example. Dimension d₂ comprises about 10 μm toabout 350 μm, in some embodiments. Alternatively, dimension d₂ maycomprise other values and other relative values.

FIG. 20 is a cross-sectional view illustrating a shear force test of aconnector 158 comprising solder ball coupled to a through-via 106/112 ofa package in accordance with some embodiments. The connector 158 iscoupled to the through-via 106/112 of a packaged semiconductor device150 described herein through an opening 142 in the insulating material104. A tool 172 is used to test the shear force of the connector 158coupled to the through-via 106/112 by exerting lateral pressure on theconnector 158. Experimental results of embodiments of the presentdisclosure showed increased ball strength and a greater shear stressrequired for a failure of the solder joint. Because a portion of theinsulating material 104 resides on a top surface over edges of thethrough-vias 106/112, a recess proximate the molding material 130 isprevented from forming, which results in an increased strength of theconnection of the connector 158 to the through-via 106/112,advantageously.

FIGS. 21 and 22 are top views and cross-sectional views, respectively,of portions of a packaged semiconductor device 150 in accordance withsome embodiments. FIG. 21 is an image of a connector 158 coupled to athrough-via 106/112 in accordance with some embodiments. No recess isformed between the through-via 130 and the molding material 130; rather,the edges of the insulating material 104 are directly adjacent thethrough-vias 106/112. No portion of the molding material 130 is visiblein the top view.

FIG. 22 is a drawing reproduction of a cross-sectional scanning electronmicroscope (XSEM) image of a region of a packaged semiconductor device150 proximate an opening 142 in the insulating material 104, which showsa well-sealed area proximate the through-via 106/112, the connector 158,the molding material 130, and the insulating material 104. The connector158 is well-attached to the insulating material 104. A recess is notformed between the through-via 106/112 and the molding compound 130,advantageously.

FIG. 23 is a cross-sectional view illustrating a packaged semiconductordevice 150 in accordance with some embodiments. The protective film 140is included in the package, disposed over the insulating material 104.The openings 142″ are formed in the insulating material 104 and also theprotective film 140. Removing the portion of the insulating material 104proximate each of the plurality of through-vias 106/112 furthercomprises removing a portion of the protective film 140 proximate eachof the plurality of through-vias 106/112 in some embodiments, forexample.

FIG. 23 also illustrates some embodiments wherein the openings 142″ inthe insulating material 104 (and also in the protective film 140)comprise substantially straight sidewalls 146″. The sidewalls 146, 146′,and 146″ of the openings 142, 142′, and 142″ in the insulating material104 comprise a shape such as tapered (shown in FIG. 19 at 146),substantially straight (FIG. 23 at 146″), stair-stepped (FIG. 19 at146′), and/or a combination thereof in some embodiments of the presentdisclosure, for example. The sidewalls 146, 146′, and 146″ of theopenings 142, 142′, and 142″ in the insulating material 104 mayalternatively comprise other shapes.

FIG. 24 is a flow chart 180 illustrating a method of packaging asemiconductor device in accordance with some embodiments. In step 182,through-vias 106/112 (see also FIGS. 1 through 7) are coupled to aninsulating material 104, each of the through-vias 106/112 having a firstwidth d₁ (FIG. 19). In step 184, dies 120 are coupled to the insulatingmaterial 104 (FIG. 8). In step 186, a portion of the insulating material104 proximate each of the through-vias 106/112 is removed, wherein theportion of the insulating material 104 proximate each of thethrough-vias 106/112 removed has a second width d₂, the second width d₂being less than the first width d₁ (FIGS. 15 and 19).

Some embodiments of the present disclosure include methods of packagingsemiconductor devices. Other embodiments include packaged semiconductordevices 150 and/or 170 that have been packaged using the novel methodsdescribed herein.

Some advantages of embodiments of the present disclosure includeproviding packaging methods and structures wherein openings in aninsulating material over through-vias have a smaller width than thethrough-vias. The openings in the insulating material having a smallerwidth than the through-vias prevents a recess from forming between amolding material and the through-vias, which improves reliability andeliminates water vapor from entering into such a recess. A gap betweenconnectors comprising solder balls, the insulating material, and themolding material is prevented from forming. Because the recess is notformed between the molding material and the through-vias, controllingthe depth of the recess is not an issue.

Furthermore, uniformity of solder paste that is applied to the topsurfaces of the through-vias is improved, due to the prevention of therecess forming between the molding material and the through-vias. Thesolder paste is only formed on top surfaces of the through-vias. Thesolder paste is not formed on sidewalls of the through-vias, which arecovered by the molding material, for example. Overlay (OVL) performanceis also improved.

The novel packaging structures and methods are implementable in and areparticularly beneficial for wafer level packaging (WLP) or chip scalepackaging (CSP) techniques and processes. Furthermore, the novelpackaging methods and structures described herein are easilyimplementable in manufacturing and packaging process flows.

In some embodiments, a method of packaging a semiconductor deviceincludes coupling a plurality of through-vias to an insulating material,each of the plurality of through-vias comprising a first width, andcoupling a plurality of dies to the insulating material. The methodincludes removing a portion of the insulating material proximate each ofthe plurality of through-vias, wherein the portion of the insulatingmaterial proximate each of the plurality of through-vias removedcomprises a second width, the second width being less than the firstwidth.

In other embodiments, a method of packaging a semiconductor deviceincludes forming an insulating material over a carrier, and coupling aplurality of through-vias to the insulating material. Each of theplurality of through-vias comprises a first width. The method includescoupling a plurality of dies to the insulating material, and disposing amolding material around the plurality of through-vias, around theplurality of dies, and between the plurality of through-vias and theplurality of dies. An interconnect structure is formed over theplurality of through-vias, the plurality of dies, and the moldingmaterial. The carrier is removed, and a portion of the insulatingmaterial proximate each of the plurality of through-vias is removed. Theportion of the insulating material proximate each of the plurality ofthrough-vias removed comprises a second width, the second width beingless than the first width. The insulating material, the moldingmaterial, and the interconnect structure are diced to form a pluralityof packaged semiconductor devices.

In other embodiments, a packaged semiconductor device includes anintegrated circuit die, a molding material disposed around theintegrated circuit die, and a plurality of through-vias disposed withinthe molding material. Each of the plurality of through-vias comprises afirst width. An insulating material is disposed on a first side of theintegrated circuit die, the molding material, and a first portion ofeach of the plurality of through-vias. An interconnect structure isdisposed on a second side of the integrated circuit die, the moldingmaterial, and the plurality of through-vias. A second portion of each ofthe through-vias is exposed through openings in the insulating material.The openings in the insulating material comprise a second width, thesecond width being less than the first width.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A method of packaging a semiconductor device, themethod comprising: forming an insulating layer on a substrate; afterforming the insulating layer, forming a plurality of through-vias on theinsulating layer, each of the plurality of through-vias comprising afirst width, the first width measured in a direction parallel to atopmost surface of the insulating layer, and extending from the topmostsurface of the insulating layer by a distance greater than the firstwidth; coupling a plurality of dies to the insulating layer; removingthe substrate; forming a protective film adjacent the insulatingmaterial after removing the substrate; removing a portion of theinsulating layer proximate each of the plurality of through-vias toexpose a portion of each of the plurality of through-vias, each exposedportion having a second width, the second width being less than thefirst width, the second width measured in the direction parallel to themajor plane of the insulating layer, wherein removing the portion of theinsulating material further comprises removing a portion of theprotective film; and forming solder paste over the exposed portion ofeach of the plurality of the through-vias.
 2. The method according toclaim 1, further comprising forming a molding material around theplurality of through-vias, around the plurality of dies, and between theplurality of through-vias and the plurality of dies.
 3. The methodaccording to claim 2, wherein coupling the plurality of through-vias tothe insulating layer and coupling the plurality of dies to theinsulating layer comprises coupling a first side of the plurality ofthrough-vias and the plurality of dies, and wherein the method furthercomprises forming an interconnect structure over a second side of theplurality of through-vias and the plurality of dies, the second sidebeing opposite the first side.
 4. The method according to claim 3,further comprising coupling a plurality of connectors to theinterconnect structure.
 5. The method according to claim 3, whereinforming the interconnect structure comprises forming fan-out regions. 6.The method according to claim 1, wherein each through-via of theplurality of through-vias has a width that is substantially uniform froma topmost edge of the through-via to a bottommost edge of thethrough-via, each of the plurality of through-vias extending along amajor axis that is longer than the first width and substantiallyperpendicular to the first width.
 7. The method according to claim 1,wherein the forming the protective film is performed at least in partwith a lamination process.
 8. The method according to claim 1, whereinthe protective film has a thickness of between about 1 μm and about 100μm.
 9. A method of packaging a semiconductor device, the methodcomprising: forming an insulating material over a carrier, theinsulating material having a planar topmost surface; after forming theinsulating material, forming on and extending outward from the planartopmost surface of the insulating material a plurality of through-vias,each of the plurality of through-vias comprising a first width; couplinga plurality of dies to the insulating material; disposing a moldingmaterial around the plurality of through-vias, around the plurality ofdies, and between the plurality of through-vias and the plurality ofdies; forming an interconnect structure over the plurality ofthrough-vias, the plurality of dies, and the molding material; removingthe carrier; forming a protective film over the insulating material,after removing the carrier; removing a portion of the insulatingmaterial proximate each of the plurality of through-vias, wherein theportion of the insulating material proximate each of the plurality ofthrough-vias removed comprises a second width, the second width beingless than the first width, wherein removing the portion of theinsulating material proximate each of the plurality of through-viasfurther comprises removing a portion of the protective film proximateeach of the plurality of through-vias; and dicing the insulatingmaterial, the molding material, and the interconnect structure to form aplurality of packaged semiconductor devices.
 10. The method according toclaim 9, wherein coupling the plurality of through-vias to theinsulating material comprises a process selected from the groupconsisting essentially of a plating process, a subtractive etch process,a damascene process, and combinations thereof.
 11. The method accordingto claim 10, wherein coupling the plurality of through-vias to theinsulating material comprises a plating process, and wherein the platingprocess comprises: forming a seed layer over the insulating material;forming a sacrificial material over the seed layer; patterning thesacrificial material; plating a conductive material over the seed layerthrough the patterned sacrificial material; removing the sacrificialmaterial, leaving portions of the seed layer exposed between theconductive material; and removing the exposed portions of the seedlayer.
 12. The method according to claim 9, wherein disposing themolding material around the plurality of through-vias and the pluralityof dies comprises forming the molding material over the plurality ofthrough-vias and the plurality of dies, and wherein the method furthercomprises removing a top portion of the molding material from over theplurality of through-vias and the plurality of dies.
 13. The methodaccording to claim 12, wherein removing the top portion of the moldingmaterial comprises a grinding process or a chemical-mechanical polishing(CMP) process.
 14. The method according to claim 9, wherein removing theportion of the insulating material proximate each of the plurality ofthrough-vias comprises a laser process.
 15. The method according toclaim 9, wherein each through-via of the plurality of through-vias has awidth that is substantially uniform from a topmost edge of thethrough-via to a bottommost edge of the through-via, each of theplurality of through-vias extending along a major axis that is longerthan the first width and substantially perpendicular to the first width.16. The method according to claim 9, wherein the insulating material isformed directly on the carrier with the planar topmost surface facingaway from the carrier.
 17. A method of manufacturing a packagedsemiconductor device, the method comprising: providing an integratedcircuit die on an insulating material over a substrate; dispensing amolding material disposed around the integrated circuit die, whereinafter the dispensing the molding material a plurality of through-viasare disposed within the molding material, each of the plurality ofthrough-vias comprising a constant first width of conductive material aseach of the plurality of through-vias extend from a first side of themolding material to a second side of the molding material, the firstwidth measured from a first sidewall of the molding material to a secondsidewall of the molding material; removing the substrate; depositing aprotective film adjacent the insulating material after the removing thesubstrate; removing a portion of the insulating material proximate eachof the plurality of through-vias to expose a portion of each of theplurality of through vias, each exposed portion having a second width,the second width being less than the first width, wherein the removingthe portion of the insulating material further comprises removing aportion of the protective film; forming an interconnect structuredisposed on a second side of the integrated circuit die, the moldingmaterial, and the plurality of through-vias, the interconnect structurehaving a first end in physical contact with a contact pad on theintegrated circuit die and a second end in physical contact with atleast one through-via of the plurality of through-vias, the second endbeing electrically continuous with the first end; and forming aplurality of connectors coupled to respective ones of the plurality ofthrough-vias through the insulating material, wherein the plurality ofconnectors each comprises a solder ball and an intermetallic compound.18. The method of claim 17, wherein the insulating material comprises amaterial selected from the group consisting essentially of a solderresist (SR), polyimide (PI), polybenzoxazole (PBO), and combinationsthereof.
 19. The method of claim 17, wherein sidewalls of the openingsin the insulating material comprise a shape selected from the groupconsisting essentially of tapered, substantially straight,stair-stepped, and combinations thereof.
 20. The method of claim 17,wherein the forming the interconnect structure comprises forming apost-passivation interconnect (PPI) structure or a redistribution layer(RDL).
 21. The method of claim 17, wherein the dispensing the moldingmaterial dispenses the molding material around and between a pluralityof integrated circuit dies, and wherein the interconnect structure isdisposed over the plurality of the integrated circuit dies and themolding material.
 22. The method of claim 17, further comprising apackaged semiconductor device electrically coupled to the plurality ofconnectors.
 23. The method of claim 17, wherein each through-via extendsalong a major axis that is longer than the first width and substantiallyperpendicular to the first width.
 24. The method of claim 17, whereineach of the plurality of through-vias being a solid conductive materialextending continuously from the first sidewall of the molding materialto the second sidewall of the molding material.